The present invention relates to memory devices and methods of fabrication therefor, and more particularly, to ferroelectric memory devices and methods of fabrication therefor.
Typical ferroelectric memory devices can retain data even when de-energized. Similar to DRAMs and SRAMs, ferroelectric memory devices typically operate with a low power supply voltage. Thus, ferroelectric devices are attractive for use in smart cards or the like.
A conventional method of fabricating a ferroelectric memory device will be described with reference to FIG. 1 through FIG. 3. Referring now to FIG. 1, a device isolation layer 13 is formed in a predetermined area of a semiconductor substrate 11 to define an active region. A plurality of insulated gate electrodes 15, i.e., local word lines, is formed across the active region and the device isolation layer 13. Thereafter, impurities are implanted into the active region between the gate electrodes 15 to form source/drain regions 17s and 17d. A first lower interlayer insulating layer 19 is formed on the resultant structure. The first lower interlayer insulating layer 19 is patterned to form storage node contact holes that expose the source regions 17s. Contact plugs 21 are then formed in the storage node contact holes.
Referring to FIG. 2, ferroelectric capacitors 32 are arrayed on the contact plugs 21. Each of the ferroelectric capacitors 32 is composed of a bottom electrode 27, a ferroelectric layer 29, and a top electrode 31. Each of the bottom electrodes 27 covers a respective contact plug 21. A first upper interlayer insulating layer 33 is formed on the ferroelectric capacitors 32. A plurality of main word lines 35, which are local gate lines 15, are then formed on the first upper interlayer insulating layer 33. Each of the main word lines 35 generally controls four local word lines 15.
Referring now to FIG. 3, a second upper interlayer insulating layer 37 is formed on the main word lines 35. The second and first interlayer insulating layers 37 and 33 are patterned to form via holes 39 that expose the top electrodes 31. A plurality of plate lines 41 are formed that contact the top electrodes 31 through the via holes 39. The plate lines 41 are arranged to be parallel with the word lines 35.
To reduce an aspect ratio of each of the via holes 39, wet and dry etch techniques can be used. In this case, the via hole 39 tends to have an inclined upper sidewall 39a, as shown in FIG. 3. Unfortunately, excessive wet-etch may result in exposure of the main word lines 35.
As another approach to reduce an aspect ratio of the via hole 39, the diameter of the via hole 39 can be increased. However, a spacing between the via hole 39 and an adjacent main word line 35 tends to decrease with an increase in integration level. This makes precise alignment during a photo process for forming the via hole 39 desirable.
According to the foregoing prior art, decreasing an aspect ratio of the via holes leads to a strong probability that the main word lines will be exposed. Therefore, it is hard to avoid an electric short between the plate line and the main word line as well as a contact failure between the top electrode and the plate line.